The present invention relates generally to the field of semiconductor devices; and, more particularly, to a method of maintaining or increasing the channel length while reducing small device dimensions to eliminate short channel effects of corner devices.
An integrated circuit (IC) is an assembly of discrete devices such as resistors, transistors, capacitors, etc. The transistor is a device comprising on-off properties that act as a power switch to the IC. A commonly known transistor to those skilled in the art is a field effect transistor (FET), or more particularly, a metal-oxide-semiconductor field effect transistor (MOSFET).
Generally speaking, a typical FET comprises a silicon substrate with a thin layer of thermally grown oxide used to isolate the substrate from a gate electrode. The thin layer of oxide is referred hereafter as gate oxide. The gate electrode controls the on-off properties of the working device. The material of the gate electrode is typically polycrystalline silicon capped with a metal layer such as a silicide. A low resistance of the gate electrode is critical to enhance a current flow of the carriers between two regions adjacent to the gate electrode called the xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d. The source and drain are regions that have been implanted with impurities, also referred to as dopants. Depending on the type of device structure, boron or phosphorous are commonly used as the dopants. For example, if the device is a P-MOS transistor, the source and drain are doped P+ with boron.
A threshold voltage is applied to the gate electrode and charges the gate electrode to be either negative or positive. In the case the gate electrode is positively charged, the negatively charged electrons in the gate oxide are attracted to the interface of the gate electrode and the gate oxide. Accordingly, the positively charged atoms in the gate oxide are repelled to the interface of the gate oxide and the wafer substrate. Further, in the case where the silicon substrate is doped with N-well, the negative charges in the wafer substrate are attracted to the surface of the substrate. These negative charges create a channel for a current of the carriers to flow between the source to the drain. The channel length (L) is often dictated by the length of the gate electrode.
To achieve higher operating speeds and increased packing densities, the FET device structures continue to shrink below the quarter micron size. The decrease in device dimensions leads to reduced channel lengths, which results in major modifications in the observed device characteristics. The short-channel effects, for example, include shifts in the threshold voltage and an increase in the subthreshold current. The shift in the threshold voltage results in a pinch in the carrier channel described previously so that the flow is cut short before reaching the drain. The shift in the subthreshold current affects the off-state power dissipation, dynamic logic clock speeds, and memory refresh times. The threshold voltage becomes a function of the gate dimensions which often dictates the channel length in smaller devices. In a short channel device, the source and drain assist in depleting the region under the gate. As a result, less gate charge is required. For devices with long channel lengths, the threshold voltage is typically independent of the gate length and width.
To resolve the short channel effect, some methods have been used to implant the wafer substrate with dopants to provide more holes or electrons. For example, in a P-MOS transistor, the wafer substrate was slightly doped with P+ dopants, such as boron or phosphorous. As a result, the P+ dopants provided more electrons to the carrier channel. Due to the added electrons, the shift in the threshold voltage observed in a short channel effect was adjusted to be comparable with the threshold voltage commonly used in devices with large dimensions.
Determining the amount of dopants required for adjusting the threshold voltage is simply a trial and error method. This method requires many test wafers and resources to analyze and evaluate test results. Further, the electrons are typically concentrated at the corners, therefore, the corners of the transistor have a lower threshold voltage than the main transistor where the carrier current flows. The lower threshold voltage at the corners is still observed after readjusting the threshold voltage by doping impurities.
Other solutions to resolve the short channeling effect involved a different etch process to modulate the profile of the active area. Generally, the profile of the active area edge was very steep. Attempts to make the profile more sloped required a great number of test wafers and cross section results. It is desired to fabricate semiconductor devices using reliable, cost-efficient methods to increase the semiconductor device speed and to maintain or enhance the IC performance, as the device structures continue to scale down below the quarter micron size.